In this thesis, I present development details and test results for the ONSEN system, a novel real-time data-processing system that will perform an online reduction of the output data from the Belle II pixel detector. The Belle II experiment will be located at the future SuperKEKB electron-positron collider. With its 40 sensor modules, arranged in a two-layer barrel geometry directly around the beam pipe, the pixel detector will be Belle II´s innermost detector. It is subject to a harsh background environment, caused by its distance of only 14 mm from the interaction point and SuperKEKB´s unprecedented instantaneous luminosity of 8×10^35 cm^-2 s^-1. The read-out of its almost 8 million pixels takes approximately 20 microseconds, corresponding to about 5000 electron-positron bunch crossings. During this long integration time, hits in up to 3 % of all pixels will be accumulated, mostly stemming from background processes. The resulting output data rate will be close to 20 GB/s. The common data-acquisition system, used for all other Belle II subdetectors, was designed for much smaller rates and cannot be adapted to incorporate the pixel detector. An online data-reduction mechanism, based on regions of interest from a real-time event reconstruction, will be used to eliminate background hits from the pixel data and thereby reduce its size by a factor of 30 before it is put to permanent storage.The ONSEN system is responsible for the buffering of the complete pixel-detector data while the event reconstruction takes place, and for performing the filtering of pixels according to the regions of interest determined by two external systems. Its FPGA-based hardware platform is a development from the IHEP in Beijing, while the FPGA firmware performing the data-processing functions was designed at the University of Gießen. A large part of the ONSEN system´s firmware is a result from the work on this thesis. This includes: the co-design of the overall system architecture; I/O mechanisms for the data exchange with other subsystems of the data-acquisition chain, using different protocols; the buffering of the raw and processed pixel data in memory; and the parsing of data streams for the extraction of event information and data-integrity tests. To this end, code in a hardware description language was developed for the processor-based FPGA architecture, allowing the online monitoring and control of the implemented logic. Additional work was invested in the the commissioning and co-debugging of the hardware platform together with the developers from the IHEP.The pixel detector and Belle II data-acquisition systems impose various requirements on the performance of the ONSEN system, including a data throughput of almost 600 MB/s and a memory bandwidth of about 1 GB/s for every of the 32 modules performing the data reduction. The ONSEN system uses high-speed serial I/O links and low-level memory-controller interfaces to achieve these values. Small-scale tests show that the performance of the implemented logic surpasses the requirements, with a maintained input data rate of 621.6 MB/s and a memory bandwidth of up to 1683 MB/s. During tests of a pixel-detector module at the DESY test-beam facility, including the scaled-down Belle II data-acquisition system, more than 20 million events were recorded with the ONSEN system. An offline analysis of the data showed that the ONSEN system´s data processing logic performed stably and without errors for these events. Further changes to the firmware are required to scale the system up to its design architecture. Feasibility tests have shown that all components for the final system are in a working state, and the required changes to the firmware will not pose a problem.
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