Development and Test of an FPGA-based Readout System of a Silicon Pixel Detector with High Bandwidth

The Online Selection Nodes (ONSEN) system is part of Belle II data acquisition and is based on FPGA technologies. It filters and reduces the recorded data from a novel Belle II Pixel Detector (PXD) in real time. The PXD is the part of the Belle II detector with the least proximity to the interaction point of the electron-positron collider SuperKEKB. The expected data rate (PXD to ONSEN) is up to 20 GB/s in total which makes data selection necessary. Therefore, Regions of Interest (RoIs) on the sensitive areas of the PXD are determined by the systems HLT and DATCON. PXD data outside any RoIs is discarded by the ONSEN. The ONSEN is expected to reduce the data rate by a factor ∼ 30 by applying RoIs (factor 10) and the rejection of complete events (factor 3). One focus of this work was on ONSEN data processing tests. Of particular interest were conditions which could lead to incorrect data processing. In test campaigns carried out at DESY in 2016 and 2017, unexpected temperature dependencies and incorrect behaviour in case of invalid data input were observed, among others. The results from the tests were used by the ONSEN developers for firmware optimisations to ensure stable data acquisition and processing at KEK, where the Belle II detector is located. Data of the test campaign at DESY from 2017 was also analysed. Using a sample of 5 million events (collected with electron beam (3 GeV) and magnetic field (1 T)), the ONSEN pixel data reduction factor was found to be 10.38 with up to three RoIs on each of the two PXD modules available for these tests and w/o event rejection. The deviation between the pixel row and column coordinates and the corresponding RoI centres in row and column direction were found to be ∼ 0.64 pixel with σ ≈ 3.41 pixel (columns, inner PXD layer), ∼ 0.92 pixel with σ ≈ 1.22 pixel (rows, inner PXD layer), ∼ 2.23 pixel with σ ≈ 0.90 pixel (columns, outer PXD layer) and ∼ 0.16 pixel with σ ≈ 0.69 pixel (rows, outer PXD layer). An ONSEN-internal RoI distribution was developed and tested using firmware adapted for the tests. At the time of this work, the ONSEN was integrated into the Belle II data acquisition systems at KEK. The distribution feature could therefore be successfully tested at trigger rates of up to 20 kHz at KEK. Other firmware adjustments addressed processing of faulty events and handling of events rejected by the HLT system.

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Development and Test of an FPGA-based Readout System of a Silicon Pixel Detector with High Bandwidth

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